In recent data transmission/reception systems used for high-speed digital communications, a serial transmission scheme of transmitting a data signal serially has become mainstream. For high-speed synchronous processing of a serially transmitted data signal, a bit phase synchronizing circuit is often used. The bit phase synchronizing circuit adjusts the phase of an inputted data signal to have a predetermined relationship with the is phase of a clock signal, to thereby ensure errorless reception of the serially transmitted data signal.
FIG. 11 shows a configuration of a bit phase synchronizing circuit. A bit change point detection circuit 101 detects the time relationship between a transition point of a data signal DT and an edge of a clock signal CK based on a data signal DT phase-adjusted by a bit phase adjustment circuit 102 and a corresponding clock signal CK, to output a phase information signal Q on the phases of the data signal DT and the clock signal CK. The bit phase adjustment circuit 102, which has a variable delay circuit (not shown) receiving the data signal DT, phase-adjusts the data signal DT based on the phase information signal Q received from the bit change point detection circuit 101. Specifically, the bit phase adjustment circuit 102 performs a phase adjustment such as delaying the data signal DT if the setup time of the data signal DT is insufficient but performing no such delay processing if the hold time of the data signal DT is insufficient. With this, the phase of the data signal DT is adjusted so that a rising change in the clock signal CK occurs at a phase of the data signal DT near the middle point between a level transition of the data signal DT and its next level transition, to enable latching of the data signal DT with the clock signal CK (see Patent Document 1, for example).    Patent Document 1: Japanese Laid-Open Patent Publication No. 4-293332